Building And Testing A Turbine Driven Hydro Generator

The theory behind hydropower is very simple: water obeys gravity and imparts the gained kinetic energy onto a turbine, which subsequently drives a generator. The devil here is, of course, in all the details, as [FarmCraft101] on YouTube is in the process of finding out as he adds a small hydro plant to his farm dam. After previously doing all the digging and laying of pipe, in this installment, the goal is to build and test the turbine and generator section so that it can be installed.

The turbine section is 3D-printed and slides onto the metal shaft, which then protrudes from the back where it connects to a 230VAC, three-phase generator. This keeps it quite modular and easy to maintain, which, as it turns out, is a very good idea. After a lot of time spent on the lathe, cutting metal, and tapping threads, the assembled bulk of the system is finally installed for its first test run.

After all that work, the good news is that the 3D-printed turbine seems to work fine and holds up, producing a solid 440 RPM. This put it over the predicted 300 RPM, but that’s where the good news ends. Although the generator produces 28 watts, it’s officially rated for 3 kW at 300 RPM. Obviously, with the small size of this AliExpress-special, the expectation was closer to 750 watts, so that required a bit of investigation. As it turns out, at 300 RPM it only produces 9 watts, so obviously the generator was a dud despite cashing out $230 for it.

Hopefully, all it takes to fix this is to order a new generator to get this hydropower setup up and running. Fortunately, it seems that he’ll be getting his money back from the dud generator, so hopefully in the next video we’ll see the system cranking out something closer to a kilowatt of power.

youtube.com/embed/kJgdpUn8ItY?…

hackaday.com/2025/12/18/buildi…

Comunicazione di servizio: sospensione definitiva dell'istanza gup.pe

Forse vi sarete accorti che abbiamo provveduto a sospendere l'istanza gup.pe. L'abbiamo fatto perché l'istanza non esiste più già da settembre ma nella cache dlla nostra istanza erano ancora presenti i suoi account.

Oggi è chiaro che gup.pe non tornerà più, ma anche se non è più un dominio federato, per evitare problemi di impersonificazione abbiamo deciso di eliminarla del tutto.

A.gup.pe era un sistema che aggiungeva funzionalità di gruppo al lato microblogging del fediverse.

Chi segue le notizie del Fediverso su @fediverso sarà già al corrente della situazione che si è creata a inizio settembre.

Il dominio a.gup.pe è stato venduto a un nuovo proprietario, che lo ha utilizzato per un sito web di spam SEO. Questo ha disabilitato la funzionalità di gruppo, rendendo improvvisamente inutilizzabile il sistema che le persone utilizzavano ancora per i gruppi. Ciò è stato possibile perché il registrar di domini .pe consentiva la vendita del dominio prima della scadenza della registrazione.

L'organizzazione dietro a.gup.pe aveva formalmente cessato l'attività nell'autunno dello scorso anno, ma il sistema era ancora operativo e attivamente utilizzato dagli utenti. Il sistema di gruppo come a.gup.pe funzionava tramite l'iscrizione di un account relativo a un determinato argomento.

Chi è rimasto orfano di gup.pe può usare altri gruppi basati su piattaforme come #Friendica, #Lemmy o #NodeBB

Per ulteriori informazioni su come usarle, potete dare un'occhiata a questo post:

informapirata.it/2025/02/03/i-…

Guppe is dead?

Hey @wmurphyrd 👋 I notice as of September 2025, the domains gup.pe and immers.space seem to have expired and a.gup.pe has been replaced with a WordPress installation full of SEO-targeted content ab...

^{mattcoxonline (GitHub)}

informapirata

2025-02-03 19:32:00

I Gruppi del Fediverso: un modo per incontrare altri utenti Mastodon, Friendica o Pixelfed in base ai loro interessi

Il Fediverso è un luogo fatto soprattutto di interazioni sociali ma rispetto ai social commerciali non è facilissimo trovare utenti che condividano i nostri stessi interessi. Ecco come giocarsi la carta dei “Gruppi”

informapirata.it/2025/02/03/i-…

#comunità #Fediverso #Friendica #gruppi #Lemmy #Mastodon

[ap_content

I Gruppi del Fediverso: un modo per incontrare altri utenti Mastodon, Friendica o Pixelfed in base ai loro interessi

Il Fediverso è un luogo fatto soprattutto di interazioni sociali ma rispetto ai social commerciali non è facilissimo trovare utenti che condividano i…

^{informapirata}

Nostalgic Camera Is A Mashup Of Analog Video Gear

These days, you get a fantastic camera with the purchase of just about any modern smartphone. [Abe] missed some of the charm of earlier, lower-quality digital cameras, though, and wanted to recreate that experience. The way forward was obvious. He built a nostalgic digital video camera from scratch!

[Abe] figured he could build the entire project around analog gear, and then simply find a way to store the video digitally, thus creating the effect he was looking for. To that end, the build is based around a small analog video camera that’s intended for use with FPV drones. It runs on 5 to 20 volts and outputs a simple composite video signal. This makes it easy to display its output on a small LCD screen, originally intended to be used with an automotive reversing camera. These were both paired with a mini video recorder module from RunCam, which can capture composite video and store it on a microSD card in 640 x 480 resolution.

These parts were quickly lashed together, with the camera sending its output to the RunCam video recorder module, which then passed it on to the screen. Everything worked as expected, so [Abe] moved on to implementing an on-screen display using the MAX7456 chip, which is built specifically for this purpose. It overlays text on the video feed to the screen as commanded by an RP2040 microcontroller. Once that was all working, [Abe] just had to provide a battery power supply and wrap everything up in a nice retro-styled case. Then, at the last minute, the separate camera and recorder modules were replaced by a TurboWing module that combined both into one.

The result is a nifty-looking camera that produces grainy, slurry, old-school digital video. If you love 640 x 480 as a resolution, you’ll dig this. It’s got strong 90s camcorder vibes, and that’s a very good thing.

We love a good custom camera around these parts, especially those that offer deliciously high resolution. If you’re building your own, be sure to let us know. Video after the break.

youtube.com/embed/_3n2b0EUI8c?…

hackaday.com/2025/12/18/nostal…

Google presenta Gemini 3 Flash, il nuovo modello di intelligenza artificiale

La battaglia per la leadership nell’intelligenza artificiale si sta spostando sempre più dai laboratori alla produzione di massa. Il giorno dopo il rilascio di OpenAI GPT Image 1.5, Google ha presentato il modello Gemini 3 Flash e ha iniziato a renderlo predefinito nelle sue app consumer, nonché nella modalità AI nella ricerca.

Questo nuovo modello sostituisce Gemini 2.5 Flash, rilasciato solo sei mesi prima.

Google afferma che Gemini 3 Flash ha migliorato significativamente ragionamento, multimodalità ed efficienza, mantenendo al contempo una bassa latenza.

Nei primi test, il modello si è avvicinato ai sistemi “di frontiera” di Google e OpenAI. Ad esempio, nel benchmark Humanity’s Last Exam, ha ottenuto un punteggio del 33,7% senza strumentazione, rispetto al 37,5% di Gemini 3 Pro, all’11% di Gemini 2.5 Flash e al 34,5% di GPT-5.2, rilasciato di recente da OpenAI. Nel test multimodale MMMU-Pro , Gemini 3 Flash ha ottenuto un punteggio dell’81,2%, che secondo Google è il miglior risultato tra i suoi concorrenti in questa categoria.

Nonostante le prestazioni migliorate, Google posiziona Flash come un modello “veloce”. L’azienda afferma che supera Gemini 2.5 Pro, con una velocità di esecuzione circa tre volte superiore e un consumo medio di circa il 30% in meno di token nelle attività di ragionamento, riducendo potenzialmente i costi di implementazione.

Per gli utenti abituali, Gemini 3 Flash è già diventato una funzionalità standard dell’app Gemini in tutto il mondo, mentre Gemini 3 Pro rimane disponibile per attività matematiche e di programmazione più complesse.

Google sta inoltre enfatizzando gli scenari multimodali: caricamento di brevi video per consigli e coaching, invio di schizzi per il riconoscimento e utilizzo di audio per analisi o creazione di quiz. Si nota inoltre che il modello suggerisce più spesso “risposte visive”, incluse immagini e tabelle, e aiuta a creare semplici prototipi di app direttamente all’interno dell’interfaccia Gemini sulla base di query di testo.

Nella ricerca, Google sta simultaneamente ampliando l’accesso a funzionalità avanzate: Gemini 3 Pro è ora disponibile per tutti gli utenti negli Stati Uniti e anche l’adozione del suo modello proprietario di generazione di immagini Nano Banana Pro nella ricerca è aumentata. In ambito aziendale, Google sta parlando dell’adozione di Gemini 3 Flash da parte di aziende come JetBrains, Figma, Cursor, Harvey e Latitude, e il modello stesso è disponibile tramite Vertex AI e Gemini Enterprise.

Agli sviluppatori è stato promesso l’accesso a un’anteprima tramite API e l’integrazione con Antigravity, uno strumento di programmazione rilasciato da Google il mese scorso.

Google ha fissato il prezzo dell’API a 0,50 dollari per milione di token in input e 3,00 dollari per milione di token in output, leggermente più costoso di Gemini 2.5 Flash, ma l’azienda attribuisce questo risultato a un miglioramento della qualità.

Google afferma inoltre che, dal rilascio della serie Gemini 3, oltre mille miliardi di token vengono elaborati tramite la sua API al giorno. In questo contesto, la concorrenza con OpenAI si sta intensificando: all’inizio di dicembre, alcune pubblicazioni hanno riportato la nota interna “Code Red” di Sam Altman a seguito di un calo del traffico di ChatGPT dovuto alla crescita della quota di Google.

Successivamente, OpenAI ha rilasciato GPT-5.2 e un nuovo modello di generazione di immagini, affermando che il volume dei messaggi di ChatGPT era aumentato di otto volte da novembre 2024.

L'articolo Google presenta Gemini 3 Flash, il nuovo modello di intelligenza artificiale proviene da Red Hot Cyber.

Chip Swap Fixes a Dead Amiga 600

The Amiga 600 was in its day the machine nobody really wanted — a final attempt to flog the almost original spec 68000 platform from 1985, in 1992. Sure it had a PCMCIA slot nobody used, and an IDE interface for a laptop hard drive, but it served only to really annoy anyone who’d bought one when a few months later the higher-spec 1200 appeared. It’s had a rehabilitation in recent years though as a retrocomputer, and [LinuxJedi] has a 600 motherboard in need of some attention.

As expected for a machine of its age it can use replacement electrolytic capacitors, and its reset capacitor had bitten the dust. But there’s more to that with one of these machines, as capacitor leakage can damage the filter circuitry surrounding its video encoder chip. Since both video and audio flow through this circuit, there was no composite video to be seen.

The hack comes in removing the original chip rather than attempt the difficult task of replacing the filter, and replacing it with a different Sony chip in the same series. It’s nicely done with a connector in the original footprint, and a small daughterboard. The A600 lives again, but this time it won’t be a disappointment to anyone.

If you want to wallow in some Amiga history as well as read a rant about what went wrong, we have you covered.

hackaday.com/2025/12/18/chip-s…

Bare Metal STM32: Increasing the System Clock and Running Dhrystone

When you start an STM32 MCU with its default configuration, its CPU will tick along at a leisurely number of cycles on the order of 8 to 16 MHz, using the high-speed internal (HSI) clock source as a safe default to bootstrap from. After this phase, we are free to go wild with the system clock, as well as the various clock sources that are available beyond the HSI.

Increasing the system clock doesn’t just affect the CPU either, but also affects the MCU’s internal buses via its prescalers and with it the peripherals like timers on that bus. Hence it’s essential to understand the clock fabric of the target MCU. This article will focus on the general case of increasing the system clock on an STM32F103 MCU from the default to the maximum rated clock speed using the relevant registers, taking into account aspects like Flash wait states and the APB and AHB prescalers.

Although the Dhrystone benchmark is rather old-fashioned now, it’ll be used to demonstrate the difference that a faster CPU makes, as well as how complex accurately benchmarking is. Plus it’s just interesting to get an idea of how a lowly Cortex-M3 based MCU compares to a once top-of-the line Intel Pentium 90 CPU.

Stitching The Clock Fabric

The F103’s clock tree isn’t identical to that of other families of STM32 MCUs, but the basic concepts remain the same. See the below graphic from Reference Manual 0008 for the clock tree of STM32F10x MCUs:
The clock tree of the STM32F10x MCUs. (Source: RM0008)
We can see the HSI clocked at 8 MHz, which feeds into the clock input switch (SW), from where it can provide the 8 MHz system clock without further fuss. Our other options are to use the HSE, which is fed in via its respective oscillator pins and from there is wired to the same switch as the HSI. If we want to get a higher clock speed than what the HSI or HSE can provide directly, we need to use the Phase Locked Loop (PLL) to generate a higher clock speed.

For this we need to first configure the PLL, enable it and select it as the input source for the clock switch. Before we can throw the switch, however, we also need to make sure that the prescalers for the buses (APB1, APB2, AHB) are set correctly. As we can see in the clock tree diagram, we have maximum speeds for each bus and fixed scaling numbers for each prescaler.

This pattern continues with individual peripherals, some of which also have their own prescaler – like USB and the ADC – but this is just something to keep in mind for when using these peripherals. If we’re just trying to crank the CPU core up to its maximum speed and still want to use the UART, all we need is to get the PLL configuration right, along with the AHB and APB prescalers so that the UART peripheral can be interacted with.

Plugging In Numbers

Before we start happily punching numbers on our keyboard to make the MCU go faster, there’s one tedious detail that we have take care of first: appeasing the Flash memory so that it can keep up. This involves configuring the right number of wait states, the use of prefetching and similar options. For this we open our copy of RM0008 to page 60 to ogle at the FLASH_ACR register and its options.

In this Flash access control register for the F103 and kin we get to enable or disable the prefetch buffer and the latency. Fortunately, for the latency the RM tells us exactly how many wait states we have to set here depending on our target system clock speed. For the 72 MHz that the F103 is rated for, we have to set two wait states.

Scrolling up a bit to page 58 and doing the unspeakable thing of reading the documentation, we can see that the prefetch buffer is turned on after reset by default and is best left enabled. As for the half cycle option, this is related to ‘power optimization’, which means that you will not touch this unless you know what you are doing and are sure that you need to change this.

Consequently we can configure our Flash as:
FLASH->ACR |= 2 << FLASH_ACR_LATENCY_Pos | FLASH_ACR_PRFTBE;
Next we wish to use the HSE via the PLL to get the most accurate and fastest system clock speed, which first requires enable the HSE and waiting for RCC_CR_HSERDY to change to 1 as indicate that it is ready for use.
RCC->CR & RCC_CR_HSEON
while ((RCC->CR & RCC_CR_HSERDY) == 0) {
// Handle time-out.
}
Up next is configuring the PLL, starting with setting the PLL source to HSE:
RCC->CFGR |= RCC_CFGR_PLLSRC;
Now we can configure the AHB and APB prescalers. These take the new system clock and divide it by the set number. For the F103, the 36 MHz-limited APB1 needs to be set to 2, while AHB and APB2 can run at the full 72 MHz, ergo 1.
RCC->CFGR |= 1 << RCC_CFGR_HPRE_Pos;
RCC->CFGR |= 2 << RCC_CFGR_PPRE1_Pos;
RCC->CFGR |= 1 << RCC_CFGR_PPRE2_Pos;

Final Steps

Continuing configuring of the PLL and assuming that it is currently disabled, we can now mash in its multiplier number. Unlike other STM32 families, the F1’s PLL is rather simple, with just a single multiplication factor. Since we’re using the HSE, we need to know the board that we are using and the speed that this HSE oscillates at. Taking the common ‘Blue Pill’ STM32F103 board as example, this features an 8 MHz HSE input, meaning that we have to multiply this by 9 to get the target of 72 MHz.
RCC->CFGR |= 7 << RCC_CFGR_PLLMULL_Pos;
The target PLLMUL register starts at 0x02 for a multiplier of x4, ergo we need to subtract two from our target multiplier. With that done we can enable the PLL and wait for it to stabilize:
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {
// Timeout handling.
}
Next we throw the big switch to use the PLL’s output as the system clock source and wait for the switch to complete:
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= RCC_CFGR_SW_PLL;
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) { }
We should be up and running now, leaving us just to update the global CMSIS SystemCoreClock variable with the new clock speed of 72 MHz.

Benchmarking

These certainly are Dhrystone results. (Credit: Maya Posch)
Running Dhrystone on our F103 seems like a bit of a challenge as the benchmark was created for your typical desktop and server systems. To achieve this, I took the original pre-ANSI C code for Dhrystone 2.1 and adapted it to a Nodate project. The [url=https://github.com/MayaPosch/Nodate/blob/master/examples/stm32/dhrystone/src/dhrystone.cpp]dhrystone.cpp[/url] file contains the benchmark itself, with no significant modifications other than to set up the MCU and the UART as standard output target. The number of runs is also hardcoded to be 100 million so that it doesn’t have to be punched in every time.

After compiling the benchmark and flashing it to the STM32F103 board, it seemed to take a few eternities for it to complete with so many runs. When the board’s single LED finally started doing its leisurely blinking routine to indicate completion, it turned out that 347 seconds had expired, or roughly 5.78 minutes. As can be seen in the start time, this wasn’t the first attempt, after a 10 million run completed too quickly according to the benchmark’s criteria. C’est la vie.

Annoyingly, the printf-lite implementation that I use with Nodate didn’t seem to like the 32-bit float values and were absent in the final output, so I had to do the calculations for the Dhrystones Per Second (DPS) and related MIPS (DPS / 1757) myself. Since the times() implementation’s ticks equal seconds, this was at least fairly easily, giving the following numbers:

• DPS: ~288,184.438
• MIPS: ~164.021

To see whether these numbers are at all plausible, I consulted a few lists of Dhrystone benchmark results, including one for DPS and one for MIPS. Taking into account the noise created by running it on an OS versus bare metal, my use of -Og optimization level and other differences, the placement at the level of about a Pentium 100 doesn’t seem too farfetched.

There is an official ARM Dhrystone benchmarking guide (AN273), which cites a DPS of 40,600.9 for a Cortex-M MCU running at 18.5 MHz. This would be 158,014 DPS if extrapolated linearly, but obviously not the exact board, MCU or compile flags are used, so ‘rough ballpark’ seems to be the term of the day here.

Perhaps the most interesting finding is that a lowly STM32F103 MCU can keep up with a once high-end Pentium CPU of the early 1990s, at least within the limited integer-only Dhrystone benchmark. Next target will probably be to run the more modern and extensive CoreMark on the F103 and other STM32 MCUs, to give a more holistic perspective.

hackaday.com/2025/12/18/bare-m…